论文标题
缝隙：带有subnansecond Time-Walk的带状传感器读数芯片，用于J-Parc Muon $ G-2 $/EDM实验
SliT: A Strip-sensor Readout Chip with Subnanosecond Time-walk for the J-PARC Muon $g-2$/EDM Experiment
论文作者
论文摘要
已经开发了一种名为“ SLIT”的新硅丝带读数芯片，用于测量J-PARC处的MUON异常磁矩和电偶极矩。该狭缝是在Silterra 180 nm CMOS技术中设计的，具有混合信号集成电路。模拟电路结合了传统的电荷敏感放大器，塑造放大器以及两个相同通道中的两个不同的鉴别器。数字零件包括存储记忆，事件构建块，序列化器和LVD驱动程序。狭缝的一个独特特征是零交叉体系结构的利用，该结构由CR-RC滤波器组成，然后是CR电路作为电压区分。该体系结构能够以次秒无关的时间步行生成命中信号，这是实验的主要要求。测试结果表明，$ 0.38 \ pm的时间步行为0.16 $ ns在0.5至3 MIP信号之间。等效噪声电荷为$ 1547 \ pm 75 $ $ e^{ - } $（rms）$ c _ {\ rm det} = 33 $ pf作为带状传感器电容。在测试中也证明了其他功能，例如带状传感器读数芯片。 SLIT128C满足J-Parc Muon $ G-2 $/EDM实验的所有要求。
A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and LVDS drivers. A distinct feature of the SliT is utilization of the zero-cross architecture, which consists of a CR-RC filter followed by a CR circuit as a voltage differentiator. This architecture enables to generate hit signals with subnanosecond amplitude-independent time walk, which is the primary requirement for the experiment. The test results show the time walk of $0.38 \pm 0.16$ ns between 0.5 and 3 MIP signals. The equivalent noise charge is $1547 \pm 75 $ $e^{-}$ (rms) at $C_{\rm det} = 33$ pF as a strip-sensor capacitance. Other functionalities such as a strip-sensor readout chip have also been proven in the tests. The SliT128C satisfies all requirements of the J-PARC muon $g-2$/EDM experiment.
