论文标题
节能DNN加速器的位误差鲁棒性
Bit Error Robustness for Energy-Efficient DNN Accelerators
论文作者
论文摘要
与主流硬件相比,由于节省的能量,深度神经网络(DNN)加速器在过去几年中受到了很大的关注。 DNN加速器的低压操作使得在存储量化的DNN权重的存储器中导致位级故障。在本文中,我们表明,稳健的固定点量化,重量减少和随机位误差训练(randbet)的结合可显着提高(量化)DNN权重中的随机位误差。这导致低压操作和低精度量化都可以节省高能。我们的方法在跨操作电压和加速器上概括了,如介绍的SRAM阵列中的位错误所证明的那样。我们还讨论了为什么单独减肥已经是实现鲁棒性的一种非常有效的方法。此外,我们专门讨论了有关准确性,鲁棒性和精确度的涉及权衡取舍:与经过正常训练的8位DNN相比,准确性不超过1%,我们可以将CIFAR-10上的能源消耗降低20%。即使对于4位DNN,也可以以2.5%的精度为代价,例如30%,例如30%。
Deep neural network (DNN) accelerators received considerable attention in past years due to saved energy compared to mainstream hardware. Low-voltage operation of DNN accelerators allows to further reduce energy consumption significantly, however, causes bit-level failures in the memory storing the quantized DNN weights. In this paper, we show that a combination of robust fixed-point quantization, weight clipping, and random bit error training (RandBET) improves robustness against random bit errors in (quantized) DNN weights significantly. This leads to high energy savings from both low-voltage operation as well as low-precision quantization. Our approach generalizes across operating voltages and accelerators, as demonstrated on bit errors from profiled SRAM arrays. We also discuss why weight clipping alone is already a quite effective way to achieve robustness against bit errors. Moreover, we specifically discuss the involved trade-offs regarding accuracy, robustness and precision: Without losing more than 1% in accuracy compared to a normally trained 8-bit DNN, we can reduce energy consumption on CIFAR-10 by 20%. Higher energy savings of, e.g., 30%, are possible at the cost of 2.5% accuracy, even for 4-bit DNNs.