论文标题
CNTFET QUATERNARY乘数的效率低于相应的二进制文件
CNTFET quaternary multipliers are less efficient than the corresponding binary ones
论文作者
论文摘要
我们比较了N = 1，n = 2和n = 4的最坏情况延迟，芯片面积，功率和功率延迟产品（PDP），比较了N*n第四纪数字和2N*2N*2N*2N*2N*2N*。两种乘数都使用了减少华莱士的树。具有32 nm CNTFET参数的HSPICE仿真表明，二进制实现始终更有效：1*1退出乘数比1*1位乘数（和GATE）复杂得多，并同时生成产品和携带项。即使有一半的术语，第四纪还原树的术语数量与二进制术语的数量相同，并且使用的第四纪添加剂也比二进制二进制更为复杂。与计算相同信息的二进制，第四纪乘数具有更大的最坏情况延迟，更多的功率耗散和芯片区域更多。
We compare N*N quaternary digit and 2N*2N bit CNTFET multipliers in terms of Worst case delay, Chip area, Power and Power Delay Product (PDP) for N=1, N=2 and N=4. Both multipliers use Wallace reduction trees. HSpice simulations with 32-nm CNTFET parameters shows that the binary implementations are always more efficient: the 1*1 quit multiplier is far more complex than a 1*1 bit multiplier (AND gate) and generate both product and a carry terms. Even with half number of terms, the quaternary reduction tree has the same number of terms than the binary one, and uses quaternary adders that are also more complicated than the binary ones. The quaternary multipliers have larger worst case delays, more power dissipation and far more chip areas than the binary ones computing the same amount of information.
