论文标题
SAR-ADC的高速，低功率和低偏移的基于强臂动态闩锁的比较器的设计
Design of a Strong-Arm Dynamic-Latch based comparator with high speed, low power and low offset for SAR-ADC
论文作者
论文摘要
比较器是通过Nyquist-rate和对数字转换器（ADC）的过采样类似物（ADC）来实现量化或可能采样的。因此，比较器对ADC的速度和准确性具有重大影响。这项研究为基于动态的比较器提供了修订的设计，该比较器可实现最低的延迟，最大面积效率实现，减少功率耗散和低偏移。拟议的电路是使用GDPK 45 nm标准CMOS-Process设计和模拟的，以在1.2V电源电压下操作100 MHz时钟。设计和仿真是使用Cadence Virtuoso EDA工具进行的。与原始设计相比，PDP很容易减少6％，而偏移电压降低了8 mV，而没有速度折衷。
Comparators are utilised by Nyquist-rate and oversampling analog to digital converters (ADCs) to accomplish quantization and perhaps sampling. Thus, comparators have a substantial effect on the speed and accuracy of ADCs. This study provides a revised design for a dynamic-latch-based comparator that achieves the lowest latency, maximum area-efficient realisation, reduced power dissipation, and low offset. The proposed circuit has been designed and simulated using GDPK 45 nm standard CMOS-Process to operate on 100 MHz clock, at 1.2V supply voltage. Design and simulation have been carried out using CADENCE Virtuoso EDA tool. Compared to the original design, the PDP was easily reduced by approximately by 6% with offset voltage reduced by 8 mV without speed trade-off.
